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19-4723; Rev 0; 7/09
KIT ATION EVALU BLE AVAILA
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
General Description Features
o 1-Phase Quick-PWM Controller o 0.5% VOUT Accuracy Over Line, Load, and Temperature o 7-Bit IMVP-6.5 DAC o IMVP-6.5 and GMCH Compliant o Active Voltage Positioning with Adjustable Gain o Accurate Droop and Current Limit o Remote Output and Ground Sense o Adjustable Output-Voltage Slew Rate o Power-Good Window Comparator o Current Monitor o Temperature Comparator o Drives Large Synchronous Rectifier FETs o 2V to 26V Battery Input Range o Adjustable Switching Frequency (600kHz max) o Undervoltage and Thermal-Fault Protection o Soft-Startup and Soft-Shutdown o Internal Boost Diode
MAX17528
The MAX17528 comprises 1-phase Quick-PWMTM stepdown VID power-supply controllers for Intel notebook CPUs. The Quick-PWM control provides instantaneous response to fast-load current steps. Active voltage positioning reduces power dissipation and bulk output capacitance requirements and allows ideal positioning compensation for tantalum, polymer, or ceramic bulk output capacitors. The MAX17528 is intended for two different notebook CPU/GPU core applications: either bucking down the battery directly to create the core voltage, or bucking down the +5V system supply. The single-stage conversion method allows these devices to directly step down highvoltage batteries for the highest possible efficiency. Alternatively, 2-stage conversion (stepping down the +5V system supply instead of the battery) at higher switching frequency provides the minimum possible physical size. A slew-rate controller allows controlled transitions between VID codes. A thermistor-based temperature sensor provides programmable thermal protection. A current monitor provides an analog output current proportional to the processor load current. The MAX17528 implements both the Intel IMVP-6.5 CPU core specifications (CLKEN pullup to 3.3V), as well as the Intel GMCH graphics core specifications (CLKEN = GND). The MAX17528 is available in a 32-pin, 5mm x 5mm TQFN package.
Ordering Information
PART MAX17528GTJ+ TEMP RANGE -40 C to +105 C
o o
PIN-PACKAGE 32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
Applications
IMVP-6.5 Core Power Supply Intel GMCH 2009 Intel Calpella Platforms Graphics Core Power Supply Voltage-Positioned Step-Down Converters 1-to-4 Lithium-Ion (Li+)-Cell Battery-to-CPU Core Supply Converters Notebooks/Desktops/Servers
LX 25 DH 26 PGDIN 27 VRHOT 28 TIME 29 ILIM 30 VCC 31 CCV 32 1 IMON 2 GNDS 3 FB 4 BST VDD
Pin Configuration
TOP VIEW
PGND DL D6 D5 D4 18 D3 17 16 15 14 13 D2 D1 D0 GND CLKEN SHDN PWRGD TON 12 11 10 9 5 CSP 6 SLOW 7 SKIP 8 THRM
24
23
22
21
20
19
MAX17528
PAD GND
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
THIN QFN 5mm x 5mm
________________________________________________________________ Maxim Integrated Products
CSN
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
ABSOLUTE MAXIMUM RATINGS
VCC, VDD to GND .....................................................-0.3V to +6V D0-D6 to GND..........................................................-0.3V to +6V CSP, CSN to GND ....................................................-0.3V to +6V ILIM, THRM, PGDIN, VRHOT, PWRGD to GND .......-0.3V to +6V CLKEN to GND.........................................................-0.3V to +6V SKIP, SLOW to GND.................................................-0.3V to +6V CCV, FB, IMON, TIME to GND ...................-0.3V to (VCC + 0.3V) SHDN to GND (Note 1)...........................................-0.3V to +30V TON to GND ...........................................................-0.3V to +30V GNDS, PGND to GND ...........................................-0.3V to +0.3V DL to PGND................................................-0.3V to (VDD + 0.3V) BST to GND ............................................................-0.3V to +36V LX to BST..................................................................-6V to +0.3V BST to VDD.............................................................-0.3V to +30V DH to LX ....................................................-0.3V to (VBST + 0.3V) Continuous Power Dissipation (32-pin, 5mm x 5mm TQFN) Up to +70C ..............................................................1702mW Derating above +70C ..........................................21.3mW/C Operating Temperature Range .........................-40C to +105C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10s) .................................+300C
Note 1: SHDN can be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode, which disables fault protection.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 2)
PARAMETER PWM CONTROLLER Input-Voltage Range VCC, VDD Measured at FB with respect to GNDS; includes loadregulation error (Note 3) VBOOT DAC codes from 0.8125V to 1.5000V DAC codes from 0.3750V to 0.8000V DAC codes from 0V to 0.3625V 4.5 -0.5 -7 -20 1.094 -200 A GNDS IGNDS VTIME VOUT/ VGNDS, -200mV TA = +25C VCC = 4.5V to 5.5V, ITIME = 28A (RTIME = 71.5k ) RTIME = 71.5k (12.5mV/s nominal) RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) TIME Slew-Rate Accuracy Soft-start and soft-shutdown; RTIME = 35.7k (3.125mV/s nominal) to 178k (0.625mV/s nominal) SLOW = GND, RTIME = 35.7k (12.5mV/s nominal) to 178k (2.5mV/s nominal) VGNDS +200mV 0.97 -2 1.985 -10 -15 2.000 1.00 1.100 0.1 +200 1.03 +2 2.015 +10 +15 % 5.5 +0.5 +7 mV +20 1.106 V % mV V/V A V V % SYMBOL CONDITIONS MIN TYP MAX UNITS
DC Output-Voltage Accuracy
Boot Voltage Line Regulation Error GNDS Input Range GNDS Gain GNDS Input Bias Current TIME Voltage
IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k ) VCC = 4.5V to 5.5V, VIN = 4.5V to 26V
-20
+20
-20
+20
2
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 2)
PARAMETER On-Time Minimum Off-Time TON Shutdown Input Current BIAS CURRENTS Quiescent Supply Current (VCC) ICC Measured at VCC, VSKIP = 5V, FB forced above the regulation point Measured at VDD, SKIP = GND, FB forced above the regulation point, TA = +25C Measured at VCC, SHDN = GND Measured at VDD, SHDN = GND, TA = +25C Measured at FB with respect to unloaded output voltage FB forced 25mV below trip threshold IMVP-6.5: CLKEN pullup to 3.3V with 1.9k ; measured from the time when FB reaches the boot target voltage (Note 3); the time needed for FB to reach this target voltage is based on the slew rate set by RTIME IMVP-6.5: CLKEN pullup to 3.3V with 1.9k ; measured at startup from the time when CLKEN goes low PWRGD Startup Delay GMCH: CLKEN = GND; measured from the time when FB reaches the target voltage (Note 3); the time needed for FB to reach this target voltage is based on the slew rate set by RTIME Measured at FB with respect to unloaded output voltage, 15mV hysteresis (typ) tBLANK Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) 1.5 3 mA SYMBOL t ON t OFF(MIN) VIN = 12V, VFB = 1.2V (Note 4) CONDITIONS RTON = 96.75k RTON = 200k RTON = 303.25k MIN 142 300 425 TYP 167 333 500 300 0.01 MAX 192 366 575 375 1 ns A ns UNITS
MAX17528
Measured at DH (Note 4) SHDN = GND, VIN = 26V, VCC = VDD = 0V or 5V, TA = +25C
Quiescent Supply Current (VDD) Shutdown Supply Current (VCC) Shutdown Supply Current (VDD) FAULT PROTECTION Output Undervoltage-Protection Threshold Output Undervoltage Propagation Delay IMVP-6.5 CLKEN Startup Delay (Boot Time Period, CLKEN Pullup to 3.3V with 1.9k )
IDD
0.02 15 0.01
1 30 1
A A A
VUVP tUVP
-450
-400 10
-350
mV s
tBOOT
20
60
100
s
3
5
8 ms
3
5
8
PWRGD and CLKEN (IMVP-6.5, CLKEN Pullup to 3.3V with 1.9k ) Threshold PWRGD and CLKEN (IMVP-6.5, CLKEN Pullup to 3.3V with 1.9k ) Transition Blanking Time PWRGD and CLKEN (IMVP-6.5, CLKEN Pullup to 3.3V with 1.9k ) Delay
-350
-300
-250 mV
+150
+200
+250
Measured from the time when FB reaches the target voltage (Note 3) based on the slew rate set by RTIME FB forced 25mV outside the PWRGD trip thresholds
20
s
10
s
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3
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 2)
PARAMETER IMVP-6.5 CLKEN Output Low Voltage IMVP-6.5 CLKEN High Leakage Current IMVP-6.5 CLKEN Shutdown Leakage Current PWRGD Output Low Voltage PWRGD Leakage Current VCC Undervoltage Lockout Threshold CSN Discharge Resistance in UVLO and Shutdown THERMAL PROTECTION VRHOT Trip Threshold VRHOT Delay VRHOT Output On-Resistance VRHOT Leakage Current THRM Input Leakage Thermal-Shutdown Threshold Current-Limit Threshold Voltage (Positive Adjustable) Current-Limit Threshold Voltage (Positive Default) Preset Current-Limit Threshold Voltage (Negative) Accuracy Current-Limit Threshold Voltage (Zero Crossing) CSP, CSN Common-Mode Input Range CSP, CSN Input Current ILIM Input Current DC Droop Amplifier (GMD) Offset DC Droop Amplifier (GMD) Transconductance TA = +25C TA = +25C (VCSP - VCSN) at IFB = 0 IFB/ (VCSP - VCSN); VFB = VCSN = 0.45V to 2.0V, and (VCSP - VCSN) = -15.0mV to +15.0mV t VRHOT RVRHOT I VRHOT ITHRM T SHDN Measured at THRM with respect to VCC; falling edge; typical hysteresis = 100mV THRM forced 25mV below the VRHOT trip threshold; falling edge Low state High state, VRHOT forced to 5V, TA = +25C VTHRM = 0V to 5V, TA = +25C Typical hysteresis = 15C VTIME - VILIM = 100mV VTIME - VILIM = 500mV 7 45 20 -4 1 0 -0.2 -100 -0.75 592 600 2 +0.2 +100 +0.75 608 -100 +160 10 50 22.5 13 55 25 +4 29.2 30 10 2 8 1 +100 A nA C 30.8 % s SYMBOL CONDITIONS IMVP-6.5: CLKEN pullup to 3.3V with 1.9k ; I SINK = 3mA IMVP-6.5: VPGDIN = 5V, V CLKEN = 3.3V IMVP-6.5: V SHDN = GND, V CLKEN = 3.3V I SINK = 3mA High state, PWRGD forced to 5V, TA = +25C Rising edge, 65mV typical hysteresis, VUVLO(VCC) controller disabled below this level SHDN = GND and drivers disabled (not switching) 4.05 4.27 8 2 0.01 MIN TYP MAX 0.4 4 1 0.4 1 4.48 UNITS V A A V A V
VALLEY CURRENT LIMIT AND DROOP VLIMIT VCSP - VCSN mV mV mV mV V A nA mV S
VCSP - VCSN, ILIM = VCC VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT VZERO VPGND - VLX, SKIP = VCC
4
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = 0C to +85C, unless otherwise specified. Typical values are at TA = +25C.) (Note 2)
PARAMETER GATE DRIVERS DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance DH Gate-Driver Source Current DH Gate-Driver Sink Current DL Gate-Driver Source Current DL Gate-Driver Sink Current Driver Propagation Delay DL Transition Time DH Transition Time Internal BST Switch On-Resistance CURRENT MONITOR Current-Monitor Transconductance Current-Monitor Offset Referred to V(CSP, CSN) IMON Clamp Voltage LOGIC AND I/O Logic-Input High Voltage Logic-Input Low Voltage Low-Voltage LogicInput High Voltage Low-Voltage LogicInput Low Voltage Logic-Input Current CLKEN Logic-Input High Voltage for IMVP-6.5 Startup CLKEN Logic-Input Low Voltage for GMCH VIH VIL VIHLV VILLV PGDIN PGDIN SHDN, SKIP, SLOW, D0-D6 SHDN, SKIP, SLOW, D0-D6 PGDIN, SHDN, SKIP, SLOW, D0-D6 = 0 or 5V, TA = +25C -1 2.3 1.0 0.67 0.33 +1 2.3 1.0 V V V V A V V VIMON Gm(IMON) I IMON/ (VCSP - VCSN), VCSN = 0.45V to 2.0V I IMON = 0 I IMON = -1mA 4.9 -1.0 1.05 1.10 5.0 5.1 +1.0 1.15 mS mV V RBST R ON(DH) R ON(DL) BST - LX forced to 5V High state (pullup) Low state (pulldown) DH forced to 2.5V, BST - LX forced to 5V DL forced to 2.5V DH low to DL high DL low to DH high DL falling, CDL = 3nF DL rising, CDL = 3nF DH falling, CDH = 3nF DH rising, CDH = 3nF IBST = 10mA, VDD = 5V (Note 6) High state (pullup) Low state (pulldown) 0.9 0.7 0.7 0.25 2.2 2.7 2.7 8 20 20 20 20 20 20 10 20 2.5 2.0 2.0 0.7 A A A A ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX17528
IDH(SOURCE) DH forced to 2.5V, BST - LX forced to 5V IDH(SINK) IDL(SINK) IDL(SOURCE) DL forced to 2.5V
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5
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = -40C to +105C, unless otherwise specified.) (Note 2)
PARAMETER PWM CONTROLLER Input-Voltage Range VCC, VDD Measured at FB with respect to GNDS; includes loadregulation error (Note 3) VBOOT A GNDS VTIME DAC codes from 0.8125V to 1.5000V DAC codes from 0.3750V to 0.8000V DAC codes from 0V to 0.3625V 4.5 -0.75 -10 -25 1.085 -200 VOUT/ VGNDS, -200mV VGNDS +200mV 0.95 1.98 -10 -15 VCC = 4.5V to 5.5V, ITIME = 28A (RTIME = 71.5k ) RTIME = 71.5k (12.5mV/s nominal) RTIME = 35.7k (25mV/s nominal) to 178k (5mV/s nominal) TIME Slew-Rate Accuracy Soft-start and soft-shutdown; RTIME = 35.7k (3.125mV/s nominal) to 178k (0.625mV/s nominal) SLOW = GND, RTIME = 35.7k (12.5mV/s nominal) to 178k (2.5mV/s nominal) On-Time Minimum Off-Time BIAS CURRENTS Quiescent Supply Current (VCC) FAULT PROTECTION Output Undervoltage-Protection Threshold VUVP Measured at FB with respect to unloaded output voltage IMVP-6.5, CLKEN pullup to 3.3V with 1.9k ; measured from the time when FB reaches the boot target voltage (Note 3); the time needed for FB to reach this target voltage is based on the slew rate set by RTIME -460 -340 mV ICC Measured at VCC, VSKIP = 5V, FB forced above the regulation point 3 mA t ON t OFF(MIN) VIN = 12V, VFB = 1.2V (Note 4) RTON = 96.75k RTON = 200k RTON = 303.25k Measured at DH (Note 4) 5.5 +0.75 +10 mV +25 1.115 +200 1.05 2.02 +10 +15 % V mV V/V V V % SYMBOL CONDITIONS MIN MAX UNITS
DC Output-Voltage Accuracy
Boot Voltage GNDS Input Range GNDS Gain TIME Voltage
IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k )
-20
+20
-20 142 300 425
+20 192 366 575 400 ns ns
IMVP-6.5 CLKEN Startup Delay (Boot Time Period, CLKEN Pullup to 3.3V with 1.9k )
tBOOT
20
100
s
6
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = -40C to +105C, unless otherwise specified.) (Note 2)
PARAMETER SYMBOL CONDITIONS IMVP-6.5, CLKEN pullup to 3.3V with 1.9k ; measured at startup from the time when CLKEN goes low PWRGD Startup Delay GMCH, CLKEN = GND; measured from the time when FB reaches the target voltage (Note 3); the time needed for FB to reach this target voltage is based on the slew rate set by RTIME Measured at FB with respect to unloaded output voltage, 15mV hysteresis (typ) Lower threshold, falling edge (undervoltage) Upper threshold, rising edge (overvoltage) MIN 3 MAX 8 UNITS ms
MAX17528
3
8
s
PWRGD and CLKEN (IMVP-6.5, CLKEN Pullup to 3.3V with 1.9k ) Threshold IMVP-6.5 CLKEN Output Low Voltage IMVP-6.5 CLKEN High Leakage Current PWRGD Output Low Voltage VCC Undervoltage Lockout (UVLO) Threshold THERMAL PROTECTION VRHOT Trip Threshold VRHOT Output On-Resistance Current-Limit Threshold Voltage (Positive Adjustable) Current-Limit Threshold Voltage (Positive Default Preset) Current-Limit Threshold Voltage (Negative) Accuracy CSP, CSN Common-Mode Input Range DC Droop Amplifier (GMD) Offset DC Droop Amplifier (GMD) Transconductance RVRHOT VUVLO(VCC)
-360 +140
-240 mV +260 0.4 4 0.4 V A V V
IMVP-6.5: CLKEN pullup to 3.3V with 1.9k , I SINK = 3mA IMVP-6.5 = PGDIN = 5V, V CLKEN = 3.3V I SINK = 3mA Rising edge, 65mV typical hysteresis, controller disabled below this level 4.0
4.5
Measured at THRM with respect to VCC; falling edge; typical hysteresis = 100mV Low state VTIME - VILIM = 100mV VTIME - VILIM = 500mV
29
31 8
%
VALLEY CURRENT LIMIT AND DROOP VLIMIT VCSP - VCSN 7 45 20 -5 0 (VCSP - VCSN) at IFB = 0 IFB/ (VCSP - VCSN); FB = VCSN = 0.45V to 2.0V, and (VCSP - VCSN) = -15.0mV to +15.0mV -1.0 588 13 55 25 +5 2 +1.0 612 mV mV mV V mV S
VCSP - VCSN, ILIM = VCC VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT
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7
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9k, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0-D6 set for 1.20V (D0-D6 = 0001100). TA = -40C to +105C, unless otherwise specified.) (Note 2)
PARAMETER GATE DRIVERS DH Gate-Driver On-Resistance DL Gate-Driver On-Resistance Internal BST Switch On-Resistance CURRENT MONITOR Current-Monitor Transconductance Current-Monitor Offset Referred to V(CSP, CSN) IMON Clamp Voltage LOGIC AND I/O Logic-Input High Voltage Logic-Input Low Voltage Low-Voltage LogicInput High Voltage Low-Voltage LogicInput Low Voltage CLKEN Logic-Input High Voltage for IMVP-6.5 Startup CLKEN Logic-Input Low Voltage for GMCH VIH VIL VIHLV VILLV PGDIN PGDIN SHDN, SKIP, SLOW, D0-D6 SHDN, SKIP, SLOW, D0-D6 2.3 1.0 0.67 0.33 2.3 1.0 V V V V V V VIMON Gm(IMON) I IMON/ (VCSP - VCSN), VCSN = 0.45V to 2.0V I IMON = 0 I IMON = -1mA 4.9 -1.5 1.05 5.1 +1.5 1.15 mS mV V R ON(DH) R ON(DL) RBST BST - LX forced to 5V High state (pullup) Low state (pulldown) High state (pullup) Low state (pulldown) IBST = 10mA, VDD = 5V 2.5 2.0 2.0 0.7 20 SYMBOL CONDITIONS MIN TYP MAX UNITS
Note 2: Limits are 100% production tested at TA = +25C. Maximum and minimum limits over temperature are guaranteed by design and characterization. Note 3: The equation for the target voltage VTARGET is: VTARGET = the slew-rate-controlled version of VDAC, where VDAC = 0V for shutdown, VDAC = VBOOT (IMVP-6.5) or VVID (GMCH) during startup, and VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 2). In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times can be different due to MOSFET switching speeds.
8
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Typical Operating Characteristics
(TA = +25C, unless otherwise noted. Circuit of Figure 1.)
0.9V OUTPUT EFFICIENCY vs. LOAD CURRENT
MAX17528 toc01
0.9V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17528 toc02
0.65V OUTPUT EFFICIENCY vs. LOAD CURRENT
SKIP MODE PWM MODE 90 7V EFFICIENCY (%) 80 12V
MAX17528 toc03
100 7V 12V
0.92 SKIP MODE OUTPUT VOLTAGE (V) 0.90
100
90 EFFICIENCY (%)
80
0.88 PWM MODE
70 20V 60 SKIP MODE PWM MODE 0.01 0.1 1 LOAD CURRENT (A) 10 100
70 20V
0.86
60
50
0.84 0 5 10 15 20 25 LOAD CURRENT (A)
50 0.01 0.1 1 10 LOAD CURRENT (A)
0.65V OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17528 toc04
OUTPUT EFFICIENCY vs. LOAD CURRENT
SKIP MODE PWM MODE 90 EFFICIENCY (%) 7V 12V
MAX17528 toc05
OUTPUT VOLTAGE vs. LOAD CURRENT
MAX17528 toc06
0.67
100
1.12 1.10 OUTPUT VOLTAGE (V) 1.08 1.06 1.04 1.02 1.00 PWM MODE SKIP MODE
0.66 OUTPUT VOLTAGE (V) SKIP MODE 0.65
80
0.64 PWM MODE 0.63
70 20V 60
0.62 0 2 4 6 8 10 LOAD CURRENT (A)
50 0.01 0.1 1 10 LOAD CURRENT (A)
0.98 0 2 4 6 8 10 LOAD CURRENT (A)
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17528 toc07
SWITCHING FREQUENCY vs. LOAD CURRENT
MAX17528 toc08
VOUT = 0.9V NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
IIN (PWM) SUPPLY CURRENT (mA) ICC + IDD (PWM) 10 ICC + IDD (SKIP)
MAX17528 toc09
500 450 SWITCHING FREQUENCY (kHz) 400 350 300 250 200 150 100 50 0 0.01 0.1 1 LOAD CURRENT (A) 10 VOUT = 0.65V VOUT = 0.9V SKIP MODE PWM MODE
300 250 200 150 100 50 0 SKIP MODE
100
SWITCHING FREQUENCY (kHz)
PWM MODE
1 IIN (SKIP) SKIP MODE PWM MODE 6 9 12 15 18 21 24
0.1 0.01 0.1 1 10 INPUT VOLTAGE (V) INPUT VOLTAGE (V)
100
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9
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted. Circuit of Figure 1.)
VOUT = 0.65V NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17528 toc10
NO-LOAD SUPPLY CURRENT vs. INPUT VOLTAGE
MAX17528 toc11
100 IIN (PWM) SUPPLY CURRENT (mA) 10 ICC + IDD (PWM) ICC + IDD (SKIP) 1 IIN (SKIP) SKIP MODE PWM MODE 6 9 12 15 18 21
100 IIN (PWM) ICC + IDD (PWM) 10 IBIAS (mA) ICC + IDD (SKIP) 1 IIN (SKIP) SKIP MODE PWM MODE 6 9 12 15 18 21
0.1 INPUT VOLTAGE (V)
0.1 24 INPUT VOLTAGE (V)
24
IMON CURRENT AND ERROR vs. LOAD CURRENT
20
MAX17528 toc12
IMON TRANSCONDUCTANCE DISTRIBUTION
80 +85C +25C SAMPLE SIZE = 100
MAX17528 toc13 MAX17528 toc15
75
90
16
60 PERCENTAGE (%)
70 60 50 40 30 20 10 4.90 4.92 4.94 4.96 4.98 5.00 5.02 5.04 5.06 606 5.08 608
IMON (A)
ERROR (%)
12 8
45 30
4
SKIP PWM
15
0
2
4
6
8
10
12
14
16
VCSP-N (mV)
IMON TRANSCONDUCTANCE (mS)
0.8125V OUTPUT VOLTAGE DISTRIBUTION
+85C +25C
MAX17528 toc14
Gm (FB) TRANSCONDUCTANCE DISTRIBUTION
60 50 SAMPLE PERCENTAGE (%) 40 30 20 10 0 +85C +25C SAMPLE SIZE = 100
70 SAMPLE SIZE = 100 60 SAMPLE PERCENTAGE (%) 50 40 30 20 10 0 0.8075 0.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175
590
592
594
596
598
600
602
604
OUTPUT VOLTAGE (V)
TRANSCONDUCTANCE (S)
10
______________________________________________________________________________________
610
5.10
0
0
0
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted. Circuit of Figure 1.)
IMVP-6.5 SOFT-START WAVEFORM (UP TO CLKEN)
MAX17528 toc16
IMVP-6.5 SOFT-START WAVEFORM (UP TO PWRGD)
MAX17528 toc17
IMVP-6.5 SHUTDOWN WAVEFORM
MAX17528 toc18
5V A 0 5V 0 1V C B
5V 0 5V 0 5V 0 1V
A B
5V A 0 3.3V 0 5V 0 5V B C
C
D 0 0 200s/div A. SHDN, 5V/div B. CLKEN, 5V/div C. VOUT, 500mV/div D. INDUCTOR CURRENT, 10A/div A. SHDN, 5V/div B. PWRGD, 5V/div C. CLKEN, 5V/div D 0 0 1ms/div D. VOUT, 500mV/div E. INDUCTOR CURRENT, 10A/div A. SHDN, 5V/div B. CLKEN, 3.3V/div C. PWRGD, 5V/div E 0.9V 0 0 100s/div E. DL, 5V/div D. VOUT, 1V/div F. INDUCTOR CURRENT, 5A/div
D E F
GMCH SOFT-START WAVEFORM
MAX17528 toc19
GMCH SHUTDOWN WAVEFORM
MAX17528 toc20
LOAD-TRANSIENT RESPONSE (IMVP-6.5 HFM MODE)
MAX17528 toc21
5V 5V A 0 5V 0 0.9V C 0 0 1ms/div A. SHDN, 5V/div B. PWRGD, 5V/div C. VOUT, 500mV/div D. INDUCTOR CURRENT, 10A/div A. SHDN, 5V/div B. PWRGD, 5V/div C. DL, 5V/div D 0 0 100s/div D. VOUT, 500mV/div E. INDUCTOR CURRENT, 5A/div D E B 0 5V 0 5V 0 1.0815V C A B
23A A 5.5A 0.9V 0.863V 23A C 5.5A 20s/div A. IOUT = 5.5A TO 23A, 10A/div B. VOUT, 50mV/div C. INDUCTOR CURRENT, 10A/div B
______________________________________________________________________________________
11
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted. Circuit of Figure 1.)
LOAD-TRANSIENT RESPONSE (IMVP-6.5 LFM MODE)
MAX17528 toc22
LOAD-TRANSIENT RESPONSE
MAX17528 toc23
DPRSLPVR = HIGH, SLOW = LOW, VID5 TRANSITION
MAX17528 toc24
9.5A A 3.5A 0.8375V 0.825V B
8A A 1.5A 1.0815V B 1.03V
1V A 0 1V B 0.6V
8A 9.5A 3.5A 20s/div A. IOUT = 3.5A TO 9.5A, 5A/div B. VOUT, 20mV/div C. INDUCTOR CURRENT, 10A/div C 1.5A
C C 0 20s/div A. IOUT = 1.5A TO 8A, 5A/div B. VOUT, 50mV/div C. INDUCTOR CURRENT, 5A/div A. VID5, 1V/div B. VOUT, 200mV/div IOUT = 1A 40s/div C. INDUCTOR CURRENT, 10A/div
DPRSLPVR = HIGH, SLOW = HIGH, VID5 TRANSITION
MAX17528 toc25
D0 12.5mV DYNAMIC VID CODE CHANGE
MAX17528 toc26
D2 50mV DYNAMIC VID CODE CHANGE
MAX17528 toc27
1V 0 1V
5V A 0
A
5V 0
A
B 0.6V
0.9V 0.8875V
B
0.9V
B
0.85V
C 0 40s/div A. VID5, 1V/div B. VOUT, 200mV/div IOUT = 1A C. INDUCTOR CURRENT, 10A/div
0 10s/div A. D0, 5V/div B. VOUT, 20mV/div
C
0
C
10s/div A. D2, 5V/div B. VOUT, 50mV/div C. INDUCTOR CURRENT, 2A/div
C. INDUCTOR CURRENT, 2A/div
12
______________________________________________________________________________________
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Typical Operating Characteristics (continued)
(TA = +25C, unless otherwise noted. Circuit of Figure 1.)
BIAS SUPPLY REMOVAL (UVLO RESPONSE)
MAX17528 toc29
OUTPUT OVERLOAD WAVEFORM
MAX17528 toc28
1V A 0 5V B 0 5V 0 C
5V 0.9V
A B
0 5V 0 5V 0 C D E 200s/div A. 5V BIAS SUPPLY, 5V/div D. PGOOD, 5V/div B. VOUT, 500mV/div E. INDUCTOR CURRENT, C. DL, 5V/div 10A/div
D 0 100s/div A. VOUT, 500mV/div B. PGOOD, 5V/div C. DL, 5V/div D. INDUCTOR CURRENT, 10A/div
10A 0
______________________________________________________________________________________
13
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Pin Description
PIN NAME FUNCTION Current Monitor Output. The MAX17528 IMON output sources a current that is directly proportional to the current-sense voltage as defined by: I IMON = Gm(IMON) x (VCSP - VCSN) where Gm(IMON) = 5mS (typ). The IMON current is unidirectional (sources current out of IMON only) for positive current-sense values. For negative current-sense voltages, the IMON current is zero. Connect an external resistor between IMON and VSS_SENSE to create the desired IMON gain based on the following equation: 1 IMON RIMON = 0.999V/(IMAX x R SENSE x Gm(IMON)) where IMAX is defined in the Current Monitor (IMON) section of the Intel IMVP-6.5 specification and based on discrete increments (20A, 30A, 40A, etc.,), RSENSE is the typical effective value of the current-sense element (sense resistor or inductor DCR) that is used to provide the current-sense voltage, and Gm(IMON) is the typical transconductance amplifier gain as defined in the Electrical Characteristics table. The IMON voltage is internally clamped to a maximum of 1.1V (typ). The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot directly drive large capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 1. IMON is pulled to ground when the MAX17528 is in shutdown. Remote Ground-Sense Input. Connect directly to the CPU or GMCH VSS sense pin (ground sense) or directly to the ground connection of the load. GNDS internally connects to a transconductance amplifier that adjusts the feedback voltage, compensating for voltage drops between the regulator's ground and the processor's ground. Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor, RFB, between FB and the positive side of the feedback remote sense to set the steady-state droop based on the voltage-positioning gain requirement. RFB = RDROOP/(RSENSE x GMD) 3 FB where RDROOP is the desired voltage-positioning slope, GMD = 600S typ and RSENSE is the value of the current-sense resistor that is used to provide the (CSP, CSN), current-sense voltage. If lossless sensing is used, R SENSE = RL. In this case, consider using a thermistor-resistor network to minimize the temperature dependence of the voltage-positioning slope. Droop can be disabled by shorting FB to the positive remote-sense point, but doing so increases the minimum ESR requirement of the output capacitance for stability, and FB might therefore need to be driven by a carefully designed feed-forward network. FB is high impedance in shutdown. Negative Inductor Current-Sense Input. Connect CSN to the negative terminal of the inductor current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR sensing method is used (see Figure 4). Under VCC UVLO conditions and after soft-shutdown is completed, CSN is internally pulled to GND through a 10 FET to discharge the output. Positive Inductor Current-Sense Input. Connect CSP to the positive terminal of the inductor currentsensing resistor or directly to the positive terminal of the filtering capacitor used when the lossless DCR sensing method is used (see Figure 4). Active-Low Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and slow (half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is set by the time resistance. When SLOW is forced low, the slew rate is reduced to half of the nominal slew rate. For IMVP-6.5 applications (CLKEN pullup to 3.3V with 1.9k ), the fast slew rate is not needed. Connect SLOW to GND. For GMCH 2009 applications (CLKEN = GND), connect to the system GFXDPRSLPVR signal.
2
GNDS
4
CSN
5
CSP
6
SLOW
14
______________________________________________________________________________________
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Pin Description (continued)
PIN NAME FUNCTION Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the operating mode of the MAX17528. When SKIP is forced high, the controller is immediately set to automatic pulse-skipping mode. The controller returns to forced-PWM mode when SKIP is forced low and the output is in regulation. The PWRGD upper threshold is blanked during any downward outputvoltage transition that happens when the controller is in skip mode, and stays blanked until the transition-related PWRGD blanking period is complete and the output reaches regulation. IMVP-6.5: The MAX17528 is in skip mode during startup and while in boot mode, but is in forced-PWM mode during the transition from boot mode to VID mode plus 20s, and during soft-shutdown, irrespective of the skip logic level. Connect to the system DPRSLPVR signal. GMCH 2009: The MAX17528 is in skip mode during startup, while in standby mode, and while exiting standby mode, but is in forced-PWM mode during soft-shutdown, and while entering standby mode, irrespective of the skip logic level. Connect to the system GFXDPRSLPVR signal. Comparator Input for Thermal Protection. THRM connects to the positive input of an internal comparator. The comparator's negative input connects to an internal resistive voltage-divider that accurately sets the THRM threshold to 30% of the VCC voltage. Connect the output of a resistor and thermistor-divider (between VCC and GND) to THRM with the values selected so the voltage at THRM falls below 30% of VCC (1.5V when VCC = 5V) at the desired high temperature. Switching Frequency Setting Input. An external resistor between the input power source and this pin sets the switching period (tSW = 1/f SW) according to the following equation: 9 TON t SW = 16.3pF x (RTON + 6.5k ) TON becomes high impedance in shutdown to reduce the input quiescent current. If the TON current is less than 10A, the MAX17528 disables the controller, sets the TON open fault latch, and pulls DL and DH low. Open-Drain Power-Good Output. PWRGD is high impedance after output-voltage transitions (except during power-up and power-down) if FB is in regulation. During startup, PWRGD is held low. IMVP-6.5: PWRGD continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after CLKEN goes low. GMCH 2009: PWRGD starts monitoring the FB voltage 5ms (typ) after startup (from shutdown or standby mode) is complete. PWRGD is also held low while in standby mode, and while entering and exiting standby mode. PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high impedance whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced high impedance for an additional 20s after the transition is completed. The PWRGD upper threshold is blanked during any downward output-voltage transition that happens when the MAX17528 is in skip mode, and stays blanked until the transition-related PWRGD blanking period is complete and the output reaches regulation. A pullup resistor on PWRGD causes additional finite shutdown current. Active-Low Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put the controller into the low-power 1A (max) shutdown state. During startup, the controller ramps up the output voltage at 1/8 the slew rate set by the TIME resistor to the target voltage defined by the application circuit: For IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k ), the startup target is the 1.1V boot voltage. For GMCH 2009 (CLKEN = GND), the startup target is the voltage set by the VID inputs. During the shutdown transition, the MAX17528 softly ramps down the output voltage at 1/8 the slew rate set by the TIME resistor. Forcing SHDN to 11V~13V disables UVP, thermal shutdown, and clears the fault latches.
MAX17528
7
SKIP
8
THRM
10
PWRGD
11
SHDN
______________________________________________________________________________________
15
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Pin Description (continued)
PIN NAME FUNCTION Dual-Function GMCH/IMVP-6.5 Select Input and Active-Low IMVP-6.5 CPU Clock Enable OpenDrain Output. Connect to system 3.3V supply through pullup resistors for proper IMVP-6.5 operation. CLKEN voltage has to be higher than 2.3V before SHDN is pulled high. Connect to GND to select the Intel GMCH feature set. This active-low logic output indicates when the feedback voltage is in regulation. The MAX17528 forces CLKEN low during dynamic VID transitions and for an additional 20s after the VID transition is completed. CLKEN is the inverse of PWRGD, except for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram (Figure 9). The CLKEN upper threshold is blanked during any downward output-voltage transition that happens when the MAX17528 are in skip mode, and stays blanked until the transition-related PWRGD blanking period is complete and the output reaches regulation. Analog Ground Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0-D6 inputs do not have internal pullups. These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set by the VID code indicated by the logic-level voltages on D0-D6 (see Table 2). The 1111111 code corresponds to standby mode. When this code is detected, the MAX17528 enters standby mode while in forced-PWM mode, and slews to 0V at 1/8 the slew rate set by the TIME resistor. After slewing to 0V, the IC enters skip mode (DH and DL low). If D6-D0 is changed from 1111111 to a different code, the MAX17528 exits standby mode (while in skip mode) and slews the output voltage to the target voltage set by the VID code at 1x the slew rate set by the TIME resistor. Note that the standby supply current consumed by the MAX17528 is the same as its quiescent supply current, because no analog blocks are turned off. This is necessary because of the fast wake-up requirement. Power Ground. Ground connection for the DL driver. Also used as an input to the MAX17528's zerocrossing comparator. Low-Side Gate-Driver Output. DL swings from PGND to VDD. DL is forced low after shutdown. DL is forced low in skip mode after detecting an inductor current zero-crossing. Supply Voltage Input for the DL Driver. VDD is also the supply voltage used to internally recharge the BST flying capacitor during the time DL is high. Connect VDD to the 4.5V to 5.5V system supply voltage. Bypass VDD to PGND with a 1F or greater ceramic capacitor. Boost Flying Capacitor Connection. BST provides the upper supply rail for the DH high-side gate driver. An internal switch between VDD and BST charges the flying capacitor while the low-side MOSFET is on (DL pulled high and LX pulled to ground). Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. Also used as an input to the MAX17528's zero-crossing comparator. High-Side Gate-Driver Output. DH swings from LX to BST. The controller pulls DH low in shutdown. IMVP-6.5 Power-Good Logic Input. PGDIN indicates the power status of other system rails used to power the chipset and CPU VCCP supplies. For the IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k ), the MAX17528 powers up and remains at the boot voltage (VBOOT) as long as PGDIN remains low. When PGDIN is forced high, the MAX17528 transitions the output to the voltage set by the VID code, and CLKEN is allowed to go low. If PGDIN is pulled low at any time, the MAX17528 immediately forces CLKEN high and PWRGD low and sets the output to the boot voltage. The output remains at the boot voltage until the system either disables the controller or until PGDIN goes high again. For GMCH 2009 applications (CLKEN = GND), connect PGDIN to the 5V bias supply.
12
CLKEN
13
GND
14-20
D0-D6
21 22
PGND DL
23
VDD
24
BST
25 26
LX DH
27
PGDIN
16
______________________________________________________________________________________
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Pin Description (continued)
PIN 28 NAME VRHOT FUNCTION Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at THRM goes below 1.5V (30% of VCC). VRHOT is high-impedance in shutdown. Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of the internal error-amplifier target. The sum of the resistance between TIME and GND (RTIME) determines the nominal slew rate: Slew rate = (12.5mV/s) x (71.5k /RTIME) 29 TIME The guaranteed RTIME range is between 35.7k and 178k . This nominal slew rate applies to VID transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the nominal slew rate defined above. The startup and shutdown slew rates are always 1/8 of nominal slew rate to minimize surge currents. If SLOW is high, the slew rate is reduced to 1/2 of nominal. Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP to CSN equals precisely 1/10 the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). The negative current-limit threshold is nominally -125% of the corresponding valley current-limit threshold. Connect ILIM directly to VCC to set the default current-limit threshold setting of 22.5mV (typ) nominal. Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1F minimum. Integrator Capacitor Connection. Connect a capacitor (CCCV) from CCV to GND to set the integration time constant. Choose the capacitor value according to: 16 x (CCCV/Gm(CCV)) x f SW >> 1 where Gm(CCV) = 320S (max) is the integrator's transconductance and fSW is the switching frequency set by the RTON value. The integrator is internally disabled during any downward output-voltage transition that occurs in pulse-skipping mode, and remains disabled until the transition blanking period expires and the output reaches regulation (error amplifier transition detected). Exposed Pad (Back Side) and Analog Ground. Internally connected to GND. Connect to the ground plane through a thermally enhanced via.
MAX17528
30
ILIM
31
VCC
32
CCV
--
EP (GND)
______________________________________________________________________________________
17
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
11 6 AGND 7 27 14 15 16 17 18 19 20 VALLEY CURRENT LIMIT SET BY TIME TO ILIM VLIMIT = 0.2V x R2/(R2 + R3) SLEW RATE SET BY TIME BIAS CURRENT dV/dt = 12.5mV/s x 71.5k/(R2 + R3) 30 R3 64.9k R2 5.90k CSN 3.3V RVRHOT 10k 1.9k RPWRGD 10k 10 12 28 RTHRM 7.87k VCC NTC2 100k B = 4700 R3 1k AGND 1 IMON GND EP VSS_SENSE RGND 0 GND 4 29 ILIM CSP TIME AGND CCSN OPEN AGND LOAD-LINE ADJUSTMENT: RFB = RDROOP/(RSENSE x 600s) RFB 4.53k 1% C9 1000pF THRM GNDS 2 CCCV 100pF 32 13 AGND AGND C10 1000pF AGND REMOTE-SENSE FILTERS PWR CATCH RESISTORS REQUIRED WHEN CPU NOT POPULATED AGND VSS_SENSE R14 10 R16 10 R13 10 R15 10 VCC_SENSE REMOTE-SENSE INPUTS DCR THERMAL COMPENSATION 31 R1 10 C1 1.0F AGND VDD PGDIN D0 D1 D2 D3 D4 D5 D6 LX DL PGND 25 22 NLO 21 PWR 5 PWR CCSP OPEN R11 1.50k CSENSE 0.47F NTC1 10k B = 4500 D1 R10 1.00k R12 10k COUT TON 9 RBST 0 NHI CBST 0.1F PWR L1 0.36H 0.8m 23 RTON 200k PWR SWITCHING FREQUENCY (fSW = 1/tSW): tSW = 16.3pF x (RTON + 6.5k) INPUT 7V TO 24V CIN C2 1.0F 5V BIAS INPUT
ON OFF (VRON)
SHDN SLOW SKIP
VCC
SYSTEM I/O POWER-GOOD
BST DH
24 26
CORE OUTPUT
AGND
MAX17528
PWRGD CLKEN VRHOT FB 3
8
CCV
CPU IMON C8 0.022F
R4 13.0k
AGND
PWR
Figure 1. IMVP-6.5 CPU Core Application Circuit
18 ______________________________________________________________________________________
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Table 1. IMVP-6.5 Component Selection
DESIGN PARAMETERS Circuit Input-Voltage Range Maximum Load Current (TDC Current) Transient Load Current Load Line POC Setting COMPONENTS TON Resistance (RTON) 200k (fSW = 300kHz) NEC/TOKIN MPC1055LR36 0.36H, 32A, 0.8m 120k (fSW = 500kHz) NEC/TOKIN MPC1055LR36 0.36H, 32A, 0.8m 200k (fSW = 300kHz) NEC/TOKIN MPCG0740LR42 0.42H, 20A, 1.55m Siliconix 1x Si4386DY 7.8m /9.5m (typ/max) Siliconix 1x Si4642DY 3.9m /4.7m (typ/max) 1x 470F, 6m , 2.5V SANYO 2R5TPD470M6L 10x 10F, 6V ceramic (0805) 2x 10F, 25V ceramic (1210) 6.65k 64.9k 10.0k 7.68k 1.50k 1.50k 4.02k 10k NTC B = 3380 TDK NTCG163JH103F 0.22F, 6V ceramic (0805) 200k (fSW = 300kHz) NEC/TOKIN MPC1040LR88C 0.88H, 24A, 2.3m Siliconix 1x Si4386DY 7.8m /9.5m (typ/max) Siliconix 1x Si4642DY 3.9m /4.7m (typ/max) 1x 220F, 7m , 2V SANYO 2TPF220M7L 10x 10F, 6V ceramic (0805) 2x 10F, 25V ceramic (1210) 6.65k 64.9k 5.62k 4.42k 0.806k 1.20k 15.0k 10k NTC B = 3380 TDK NTCG163JH103F 0.47F, 6V ceramic (0805) AUBURNDALE IMVP-6.5 ULV Figure 1 7V to 20V 20A (15A) 14A (10A/s) 3mV/A 20A AUBURNDALE IMVP-6.5 ULV Figure 1 5V 20A (15A) 14A (10A/s) 3mV/A 20A AUBURNDALE RENDER GMCH SV Figure 2 7V to 20V 15A (10A) 12A (10A/s) 7mV/A 20A AUBURNDALE RENDER GMCH ULV Figure 2 7V to 20V 7A (5A) 5A (10A/s) 7mV/A 20A
Inductance (L)
High-Side MOSFET (NH)
Siliconix Siliconix 1x Si4386DY 1x Si4386DY 7.8m /9.5m (typ/max) 7.8m /9.5m (typ/max) Siliconix Siliconix 2x Si4642DY 2x Si4642DY 3.9m /4.7m (typ/max) 3.9m /4.7m (typ/max) 4x 330F, 6m , 2.5V Panasonic EEFSX0D0D331XR 32x 10F, 6V ceramic (0805) 4x 10F, 25V ceramic (1210) 5.90k 64.9k 4.53k 13.0k 1.00k 1.50k 10.0k 10k NTC B = 3380 TDK NTCG163JH103F 0.47F, 6V ceramic (0805) 4x 330F, 6m , 2.5V Panasonic EEFSX0D0D331XR 32x 10F, 6V ceramic (0805) 6x 10F, 6V ceramic (0805) 5.90k 64.9k 4.53k 13.0k 1.00k 1.50k 10.0k 10k NTC B = 3380 TDK NTCG163JH103F 0.47F, 6V ceramic (0805)
Low-Side MOSFET (NL)
Output Capacitors (COUT)
Input Capacitors (CIN) TIME-ILIM Resistance (R1) ILIM-GND Resistance (R2) FB Resistance (RFB) IMON Resistance (R4) LX-CSP Resistance (R5) CSP-CSN Series Resistance (R6) Parallel NTC Resistance (R7) DCR Sense NTC (NTC1) DCR Sense Capacitance (CSENSE)
______________________________________________________________________________________
19
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
11 6 7 27 14 15 16 17 18 19 20 31 R1 10 C1 1.0F AGND VDD PGDIN D0 D1 D2 D3 D4 D5 D6 TON 9 RBST 0 NHI CBST 0.1F LX DL 30 29 R2 6.65k ILIM TIME PGND CSP 25 22 NLO 21 PWR 5 PWR CCSP OPEN 4 AGND CCSN OPEN AGND LOAD-LINE ADJUSTMENT: RFB = RDROOP/(RSENSE x 600s) RFB 10.0k 1% C9 1000pF THRM GNDS 2 CCCV 100pF 32 13 AGND GND EP VSSGFX_SENSE RGND 0 AGND C10 1000pF AGND REMOTE-SENSE FILTERS PWR CATCH RESISTORS REQUIRED WHEN CPU NOT POPULATED AGND VSSGFX_SENSE R14 10 R16 10 R13 10 R15 10 VCCGFX_SENSE REMOTE-SENSE INPUTS DCR THERMAL COMPENSATION R11 1.50k CSENSE 0.22F NTC1 10k B = 4500 D1 R10 1.50k R12 4.02k COUT PWR L1 0.42H 1.55m 23 RTON 200k PWR SWITCHING FREQUENCY (fSW = 1/tSW): tSW = 16.3pF x (RTON + 6.5k) INPUT 7V TO 24V CIN C2 1.0F 5V BIAS INPUT
ON OFF (VRON)
SHDN SLOW SKIP
VCC
VID INPUTS
BST DH
24 26
VALLEY CURRENT LIMIT SET BY TIME TO ILIM VLIMIT = 0.2V x R2/(R2 + R3) SLEW RATE SET BY TIME BIAS CURRENT dV/dt = 12.5mV/s x 71.5k/(R2 + R3) R3 64.9k
GFX OUTPUT
AGND
3.3V RVRHOT 10k RPWRGD 10k 10 12
CSN
MAX17528
PWRGD CLKEN
28 RTHRM 7.87k VCC NTC2 100k B = 4700 R3 6.2k AGND 1
VRHOT FB
3
8
CCV IMON GND
GFX IMON C8 0.022F
R4 7.68k
AGND
PWR
Figure 2. GMCH (Render Core) Application Circuit
20 ______________________________________________________________________________________
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Detailed Description
Free-Running, Constant On-Time Controllers with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator with voltage feed-forward (Figure 3). This architecture relies on the output filter capacitor's ESR and the load regulation to provide the proper current-mode compensation, so the resulting feedback ripple voltage provides the PWM ramp signal. The control algorithm is simple: the high-side switch on-time is determined solely by a one-shot whose period is inversely proportional to input voltage, and directly proportional to the feedback voltage (see the On-Time One-Shot section). Another oneshot sets a minimum off-time. The on-time one-shot triggers when the error comparator goes low (the feedback voltage drops below the target voltage), the inductor current is below the valley current-limit threshold, and the minimum off-time one-shot times out. A 96.75k to 303.25k corresponds to switching periods of 1.67s (600kHz) to 5s (200kHz), respectively. High-frequency (over 500kHz) operation optimizes the application for the smallest component size, trading off efficiency due to higher switching losses. This may be acceptable in ultra-portable devices where the load currents are lower and the controller is powered from a lower voltage supply. Low-frequency (under 300kHz) operation offers the best overall efficiency at the expense of component size and board space.
MAX17528
+5V Bias Supply (VCC and VDD) The Quick-PWM controller requires an external +5V bias supply in addition to the battery. Typically, this +5V bias supply is the notebook's 95%-efficient, +5V system supply. Keeping the bias supply external to the IC improves efficiency and eliminates the cost associated with the +5V linear regulator that would otherwise be needed to supply the PWM circuit and gate drivers. If stand-alone capability is needed, the +5V bias supply can be generated with an external linear regulator.
The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum current drawn is: IBIAS = ICC + fSW QG(LOW) + QG(HIGH)
TON Open-Circuit Fault Protection The TON input includes open-circuit protection to avoid long, uncontrolled on-times that could result in an overvoltage condition on the output. The MAX17528 detects an open-circuit fault if the TON current drops below 10A for any reason--the TON resistor (R TON ) is unpopulated, a high resistance value is used, the input voltage is low, etc. Under these conditions, the MAX17528 stops switching (DH and DL pulled low) and immediately sets the fault latch. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. On-Time One-Shot The core contains a fast, low-jitter, adjustable one-shot that sets the high-side MOSFET's on-time. The one-shot varies the on-time in response to the input and feedback voltages. The main high-side switch on-time is inversely proportional to the input voltage as measured by the RTON input, and proportional to the feedback voltage (VFB): V tON = tSW FB VIN
where the switching period (tSW = 1/fSW) is set by the resistor between VIN and TON. This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions, such as the 455kHz IF band; second, the inductor ripple-current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The on-time one-shots have good accuracy at the operating points specified in the Electrical Characteristics table. On-times at operating points far removed from the conditions specified in the Electrical Characteristics table can vary over a wider range.
(
)
where ICC is provided in the Electrical Characteristics table, fSW is the switching frequency, and QG(LOW) and Q G(HIGH) are the MOSFET data sheet's total gatecharge specification limits at VGS = 5V. VIN and VDD can be connected if the input power source is a fixed +4.5V to +5.5V supply. If the +5V bias supply is powered up prior to the battery supply, the enable signal (SHDN going from low to high) must be delayed until the battery voltage is present to ensure startup.
Switching Frequency (TON)
Connect a resistor (RTON) between TON and VIN to set the switching period (tSW = 1/fSW): tSW = 16.3pF x (RTON + 6.5k)
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21
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
CSP CSN ILIM TIME Q 10x MINIMUM OFF-TIME TRIG ONE-SHOT FB VCC REF (2.0V) R Q S GND S D0-D6 PGDIN SHDN DAC CURRENT SCALING PGND LX 1mV R VDD Q BST DH LX ON-TIME ONE-SHOT TRIG Q CURRENT MONITOR IMON Gm(IMON) 5mS
MAX17528
TON
DL
TARGET
FAULT
PGND
SKIP
REF 500k CCV Gm(CCV) 160S R REF FB CSP Gm(FB) 600S TARGET + 300mV FAULT TARGET - 300mV TARGET + 200mV SLEW_RATE
MODE CONTROL
SKIP SLOW
BLANK
CLKEN 60s STARTUP DELAY 5ms STARTUP DELAY
PWRGD
GNDS
CSN
VRHOT Gm(GNDS) TARGET - 400mV 0.3 x VCC
THRM
Figure 3. Functional Diagram
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical Characteristics table are influenced by switching delays in the external high-side MOSFET. Resistive losses, including the inductor, both MOSFETs, and printed-circuit board (PCB) copper losses in the output and ground tend to raise the switching frequency as the load current increases. Under light-load conditions, the dead-time effect increases the effective on-time, reducing the switching frequency. It occurs only during forced-PWM operation and dynamic output-voltage transitions when the inductor current reverses at lightor negative-load currents. With reversed inductor current, the inductor's EMF causes LX to go high earlier than normal, extending the on-time by a period equal to the DH-rising dead time. For loads above the critical conduction point, where the dead-time effect is no longer a factor, the actual switching frequency is: fSW = t ON (VIN + VDIS - VCHG ) requirements (RCS x IOUT(MAX) < 50mV), and the time constant of the RC network should match the inductor's time constant (L/RDCR): R2 RCS = R R1+ R2 DCR and: RDCR = L CEQ 1 1 R1 + R2
MAX17528
(VOUT + VDIS )
where VDIS is the sum of the parasitic voltage drops in the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and PCB resistances; and tON is the on-time as determined above.
Current Sense
The output current is differentially sensed by the highimpedance current-sense inputs (CSP and CSN). Lowoffset amplifiers are used for voltage-positioning gain, current-limit protection, and current monitoring. Sensing the current at the output offers advantages, including less noise sensitivity and the flexibility to use either a currentsense resistor or the DC resistance of the power inductor. Using the DC resistance (RDCR) of the inductor allows higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor's DCR must be accounted for in the output-voltage drooperror budget and current monitor. This current-sense method uses an RC filtering network to extract the current information from the inductor (see Figure 4). The resistive divider used should provide a current-sense resistance (RCS) low enough to meet the current-limit
where RCS is the required current-sense resistance, and RDCR is the inductor's series DC resistance. Use the worst-case inductance and RDCR values provided by the inductor manufacturer, adding some margin for the inductance drop over temperature and load. To minimize the current-sense error due to the current-sense inputs' bias current (ICSP), choose R1 || R2 to be less than 2k and use the above equation to determine the sense capacitance (CEQ). Choose capacitors with 5% tolerance and resistors with 1% tolerance specifications. Temperature compensation is recommended for this current-sense method. See the Voltage Positioning and Loop Compensation section for detailed information. When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC filter to eliminate the AC voltage step caused by the equivalent series inductance (LESL) of the current-sense resistor (see Figure 4). The ESL-induced voltage step does not affect the average current-sense voltage, but results in a significant peak current-sense voltage error that results in unwanted offsets in the regulation voltage and results in early current-limit detection. Similar to the inductor DCR sensing method, the RC filter's time constant should match the L/R time constant formed by the current-sense resistor's parasitic inductance: LESL = CEQR1 RSENSE where LESL is the equivalent series inductance of the current-sense resistor, R SENSE is the current-sense resistance value, CEQ and R1 are the time-constant matching components.
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23
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
INPUT (VIN) DH LX DL MAX17528 PGND CSP CSN A) OUTPUT SERIES RESISTOR SENSING NL DL R1 CEQ COUT CEQR1 = LSENSE RSENSE NH CIN L SENSE RESISTOR LESL RSENSE
INPUT (VIN) DH LX DL MAX17528 PGND NL DL R1 R2 COUT RCS = NH CIN L INDUCTOR DCR
(R1R2R2) R +
L CEQ
DCR
CSP CSN B) LOSSLESS INDUCTOR SENSING
CEQ
RDCR =
[
1 R1
+
1 R2
]
FOR THERMAL COMPENSATION: R2 SHOULD CONSIST OF AN NTC RESISTOR IN SERIES WITH A STANDARD THIN-FILM RESISTOR.
Figure 4. Current-Sense Methods
Current Limit The current-limit circuit employs a "valley" current-sensing algorithm that uses a current-sense element (see Figure 4) between the current-sense inputs (CSP to CSN) to detect the inductor current. If the differential current-sense voltage exceeds the current-limit threshold, the PWM controller does not initiate a new cycle until the inductor current drops below the valley currentlimit threshold. Since only the valley current level is actively limited, the actual peak inductor current exceeds the valley current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are a function of the current-sense impedance, inductor value, and battery voltage. When combined with the undervoltage protection circuit, this current-limit method is effective in almost every circumstance.
The positive valley current-limit threshold voltage at CSP to CSN equals precisely 1/10 of the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV current-sense range). Connect ILIM directly to VCC to set the default current-limit threshold setting of 22.5mV nominal. The negative current-limit threshold (forced-PWM mode only) is nominally -125% of the corresponding valley current-limit threshold. When the inductor current drops below the negative current limit, the controller immediately activates an on-time pulse--DL turns off, and DH turns on--allowing the inductor current to remain above the negative current threshold. Carefully observe the PCB layout guidelines to ensure that noise and DC errors do not corrupt the current-sense signals seen by the current-sense inputs (CSP, CSN).
24
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Feedback
The nominal no-load output voltage (V TARGET ) is defined by the VID-selected DAC voltage (see Table 2) plus the remote ground-sense adjustment (VGNDS) as defined in the following equation: VTARGET = VFB = VDAC + VGNDS where VDAC is the selected VID voltage. On startup, IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k) applications slew the target voltage from ground to the preset 1.1V boot voltage and GMCH (CLKEN = GND) applications slew the target voltage directly to the VID-selected DAC target. connects to an amplifier that adds an offset directly to the feedback voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. Connect the voltage-positioning resistor (RFB) and ground-sense (GNDS) input directly to the processor's remote-sense outputs as shown in Figures 1 and 2.
MAX17528
Voltage-Positioning Amplifier (Steady-State Droop) The MAX17528 includes a transconductance amplifier for adding gain to the voltage-positioning sense path. The amplifier's input is generated by the differential current-sense inputs that sense the inductor current by measuring the voltage across either current-sense resistors or the inductor's DCR. The amplifier's output connects directly to the regulator's voltage-positioned feedback input (FB), so the resistance between FB and the output-voltage sense point determines the voltagepositioning gain:
VOUT = VTARGET - RFBIFB where the target voltage (VTARGET = VFB) is defined by the selected VID code (Table 3 for IMVP6 or Table 4 for GMCH), and the FB amplifier's output current (IFB) is determined by the sum of the current-sense voltages: IFB = Gm(FB) (VCSP - VCSN ) where G m(FB) is typically 600S as defined in the Electrical Characteristics table.
Integrator Amplifier An integrator amplifier forces the DC average of the FB voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and provides a fine adjustment to the regulation voltage (Figure 3), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The integrator amplifier has the ability to shift the output voltage by 50mV (typ). The integration time constant can be set easily with an external compensation capacitor between CCV and analog ground, with the minimum recommended CCV capacitor value determined by: CCCV >> Gm(CCV)/(16 x fSW) where G m(CCV) = 320S (max) is the integrator's transconductance and fSW is the switching frequency set by the RTON resistance. The MAX17528 disables the integrator by connecting the amplifier inputs together at the beginning of all downward VID transitions done in pulse-skipping mode (SKIP = high). The integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
DAC Inputs (D0-D6)
The digital-to-analog converter (DAC) programs the output voltage using the D0-D6 inputs. D0-D6 are lowvoltage (1.0V) logic inputs designed to interface directly with the CPU. Do not leave D0-D6 unconnected. Changing D0-D6 initiates a transition to a new outputvoltage level. Change D0-D6 together, avoiding greater than 20ns skew between bits. Otherwise, incorrect DAC readings can cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with the Intel IMVP-6.5/ GMCH specifications (Table 2).
Differential Remote Sense The MAX17528 includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PCB traces and through the processor's power pins. The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Table 2. IMVP-6.5 Output Voltage VID DAC Codes
D6 D5 D4 D3 D2 D1 D0 IMVP-6.5 OUTPUT VOLTAGE (V) 1.5000 1.4875 1.4750 1.4625 1.4500 1.4375 1.4250 1.4125 1.4000 1.3875 1.3750 1.3625 1.3500 1.3375 1.3250 1.3125 1.3000 1.2875 1.2750 1.2625 1.2500 1.2375 1.2250 1.2125 1.2000 1.1875 1.1750 1.1625 1.1500 1.1375 1.1250 1.1125 1.1000 1.0875 1.0750 1.0625 1.0500 1.0375 D6 D5 D4 D3 D2 D1 D0 IMVP-6.5 OUTPUT VOLTAGE (V) 0.7000 0.6875 0.6750 0.6625 0.6500 0.6375 0.6250 0.6125 0.6000 0.5875 0.5750 0.5625 0.5500 0.5375 0.5250 0.5125 0.5000 0.4875 0.4750 0.4625 0.4500 0.4375 0.4250 0.4125 0.4000 0.3875 0.3750 0.3625 0.3500 0.3375 0.3250 0.3125 0.3000 0.2875 0.2750 0.2625 0.2500 0.2375
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
26
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Table 2. IMVP-6.5 Output Voltage VID DAC Codes (continued)
D6 D5 D4 D3 D2 D1 D0 IMVP-6.5 OUTPUT VOLTAGE (V) 1.0250 1.0125 1.0000 0.9875 0.9750 0.9625 0.9500 0.9375 0.9250 0.9125 0.9000 0.8875 0.8750 0.8625 0.8500 0.8375 0.8250 0.8125 0.8000 0.7875 0.7750 0.7625 0.7500 0.7375 0.7250 0.7125 D6 D5 D4 D3 D2 D1 D0 IMVP-6.5 OUTPUT VOLTAGE (V) 0.2250 0.2125 0.2000 0.1875 0.1750 0.1625 0.1500 0.1375 0.1250 0.1125 0.1000 0.0875 0.0750 0.0625 0.0500 0.0375 0.0250 0.0125 0 0 0 0 0 0 0 0
MAX17528
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Output-Voltage Transition Timing
The MAX17528 perform mode transitions in a controlled manner, automatically minimizing input surge currents. This feature allows the circuit designer to achieve nearly ideal transitions, guaranteeing just-in-time arrival at the new output voltage level with the lowest possible peak currents for a given output capacitance. At the beginning of an output-voltage transition, the MAX17528 blanks both PWRGD thresholds, preventing the PWRGD open-drain output and the CLKEN opendrain output from changing states during the transition. The controllers reenable the lower PWRGD threshold
approximately 20s after the slew-rate controller reaches the target output voltage. The controllers reenable the upper PWRGD threshold 20s after the slew-rate controllers reach the target output voltage only for upward VID transitions. For downward VID transitions, the MAX17528 must also detect an error amplifier transition (feedback drops below the new target threshold) before reenabling the upper PWRGD transition to avoid false PWRGD errors under pulse-skipping conditions. The slew rate (set by resistor RTIME) must be set fast enough to ensure that the transition can be completed within the maximum allotted time.
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27
1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
The MAX17528 automatically controls the current to the minimum level required to complete the transition in the calculated time. The slew-rate controller uses an internal capacitor and current-source programmed by RTIME to transition the output voltage. The total transition time depends on RTIME, the voltage difference, and the accuracy of the slew-rate controller (CSLEW accuracy). The slew rate is not dependent on the total output capacitance, as long as the surge current is less than the current limit. For all dynamic VID transitions, the transition time (tTRAN) is given by:
t TRAN =
MAX17528
where dVTARGET/dt is the required slew rate and COUT is the total output capacitance.
IMVP-6.5 Low-Power Sleep Transition
The IMVP-6.5 CPU enters a low-power state to conserve power (Figure 5). The processor enters this state by initially setting the core voltage to the LFM voltage level (no LSB stepping). Upon reaching the LFM voltage level, the processor asserts DPRLPVR, which is connected to SKIP as shown in Figure 1, signaling that a very low current state has been entered. However, the processor can still lower the core voltage by LSB increments to further reduce power consumption under this very low-power sleep state. The processor exits the sleep state by pulling DPRSLVPR low and ramping up the core voltage by LSB increments. During all VID transitions, the MAX17528 blanks PWRGD (forced high impedance) and CLKEN (forced low) until 20s after the internal target (which moves at the slew rate set by RTIME) reaches the selected VID code.
( dVTARGET / dt )
VNEW - VOLD
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the slew rate, V OLD is the original output voltage, and VNEW is the new target voltage. See TIME Slew-Rate Accuracy in the Electrical Characteristics table for slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/8. The output voltage tracks the slewed target voltage, making the transitions relatively smooth. Excluding the load current, the average inductor current required to make an output voltage transition is: IL COUT x (dVTARGET / dt)
ACTIVE VID CPU CORE VOLTAGE VID (D0-D6) DPRSLPVR PULSE SKIPPING PWRGD CLKEN DH BLANK HIGH IMPEDANCE BLANK LOW 1-PHASE FORCED PWM BLANK HIGH IMPEDANCE BLANK LOW LFM VID POSSIBLE VID CHANGE HFM VID
HFM VID
LFM VID
tBLANK 20s typ NOTE: DPRSLPVR = SKIP.
tBLANK 20s typ
Figure 5. IMVP-6.5 Sleep Transition
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
GMCH Sleep Transition
For GMCH applications (CLKEN = GND), the system enters the sleep state by stepping the VID code down to the deeper sleep VID code. During these VID transitions, the MAX17528 blanks PWRGD (forced high impedance) until 20s after the last VID transition is completed. Upon reaching the low-voltage code, the system asserts GFXDPRSLPVR, which is connected to the MAX17528 SKIP and SLOW pins as shown in Figure 2, allowing the voltage regulator to enter a pulse-skipping mode (for best light-load efficiency). Slow GMCH sleep exit: To avoid audible noise, the system reduces the exit slew rate to minimize surge currents from the input capacitors to the output capacitors. The exit transition begins by pulling GFXDPRSLPVR low, followed by LSB VID steps every 2.5s until the active VID target is reached (Figure 6). Fast GMCH sleep exit: When quickly exiting from the sleep state, the system immediately changes the VID code to the active VID code (no LSB stepping) and keeps GFXDPRSLPVR asserted to select the fast 10mV/s slew rate. Upon completion of the transition, the system pulls GFXDPRSLPVR low to signal the beginning of active state operation. During all VID transitions, the MAX17528 blanks PWRGD (forced high impedance) until 20s after the internal target (which moves at the slew rate set by RTIME) reaches the selected VID code.
MAX17528
ACTIVE VID CPU CORE VOLTAGE VID (D0-D6) GFXDPRSLPVR PULSE SKIPPING PWRGD BLANK HIGH IMPEDANCE 1-PHASE FORCED PWM BLANK HIGH IMPEDANCE DEEPER SLEEP VID
ACTIVE VID
DPRSLP VID
DH
tBLANK 20s typ NOTE: GFXDPRSLPVR = SKIP = SLOW.
tBLANK 20s typ
Figure 6. Slow Render GMCH Sleep Transition
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Forced-PWM Operation (Normal Mode)
During soft-shutdown and normal operation--when the CPU is actively running (SKIP = low, Table 3), the MAX17528 operates with the low-noise, forced-PWM control scheme. Forced-PWM operation disables the zero-crossing comparator, forcing the low-side gatedrive waveforms to constantly be the complement of the high-side gate-drive waveforms. This keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative output-voltage transitions by quickly discharging the output capacitors. Forced-PWM operation comes at a cost: the no-load +5V bias supply current remains between 10mA to 50mA, depending on the external MOSFETs and switching frequency. To maintain high efficiency under lightload conditions, the processor can switch the controller to a low-power pulse-skipping control scheme after entering suspend mode. The MAX17528 automatically uses pulse-skipping operation during soft-start, regardless of the SKIP configuration.
Light-Load Pulse-Skipping Operation
During soft-start and sleep states--SKIP is pulled high--the MAX17528 operates in pulse-skipping mode. The pulse-skipping mode enables the driver's zerocrossing comparator, so the controller pulls DL low when the low-side MOSFET voltage drop (LX to GND voltage) detects "zero" inductor current. This keeps the inductor from sinking current and discharging the output capacitors and forces the controller to skip pulses under light-load conditions to avoid overcharging the output. Upon entering pulse-skipping operation, the controller temporarily blanks the upper PWRGD and CLKEN thresholds, when the transition to pulse-skipping operation coincides with a VID code change. Once the error amplifier detects that the output voltage is in regulation, the upper PWRGD and upper CLKEN, resume tracking the selected VID DAC code. The MAX17528 automatically uses forced-PWM operation during soft-shutdown, regardless of the SKIP configuration.
10mV/s ACTIVE VID CPU CORE VOLTAGE VID (D0-D6) GFXDPRSLPVR PULSE SKIPPING PWRGD BLANK HIGH IMPEDANCE 1-PHASE FORCED PWM BLANK HIGH IMPEDANCE DEEPER SLEEP VID ACTIVE VID
DPRSLP VID
DH
tBLANK 20s typ NOTE: GFXDPRSLPVR = SKIP = SLOW.
tBLANK 20s typ
Figure 7. Fast Render GMCH Sleep Transition
30
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Automatic Pulse-Skipping Switchover In skip mode (SKIP = high), an inherent automatic switchover to PFM takes place at light loads (Figure 8). This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current's zero crossing. The zero-crossing comparator senses the inductor current across the low-side MOSFETs. Once VLX drops below the zero-crossing comparator threshold (see the Electrical Characteristics table), the comparator forces DL low (Figure 3). This mechanism causes the threshold between pulse-skipping PFM and nonskipping PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load-current is equal to 1/2 the peak-to-peak ripple current, which is a function of the inductor value (Figure 8). For a battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. The total load current at the PFM/PWM crossover threshold (ILOAD(SKIP)) is approximately:
t V V - VOUT ILOAD(SKIP) = SW OUT IN L VIN The switching waveforms might appear noisy and asynchronous when light loading activates pulse-skipping operation, but this is a normal operating condition that results in high light-load efficiency. Trade-offs between PFM noise and light-load efficiency are made by varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while higher values result in higher full-load efficiency (assuming that the coil resistance remains fixed) and less output voltage ripple. Penalties for using higher inductor values include larger physical size and degraded load-transient response, especially at low input-voltage levels.
MAX17528
Power-Up Sequence (POR, UVLO)
The MAX17528 is enabled when SHDN is driven high (Figures 9 and 10). The internal reference powers up first, followed by the analog control circuitry. Roughly 50s after the analog control circuitry powers up, the PWM controller is enabled and begins the soft-start sequence. Power-on reset (POR) occurs when VCC rises above approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system enables the controller, VCC is above 4.25V, and SHDN is driven high. The soft-start sequence ramps the output voltage up to the target voltage--either the 1.1V boot voltage for IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k) or the selected VID voltage for GMCH (CLKEN = GND)--at 1/8 the nominal slew rate set by RTIME: t TRAN(START) = 8VSTART (dVTARGET / dt)
i VBATT - VOUT = t L INDUCTOR CURRENT IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the nominal slew rate. The soft-start circuitry does not use a variable current limit, so full output current is available immediately. The MAX17528 automatically uses pulseskipping mode during soft-start and uses forced-PWM mode during soft-shutdown, regardless of the SKIP configuration. For IMVP-6.5 applications (CLKEN pullup to 3.3V with 1.9k), the MAX17528 pulls CLKEN low approximately 60s after reaching PGDIN is pulled high and the controller reaches the 1.1V boot voltage. At the same time, the MAX17528 slews the output to the selected VID voltage at the programmed nominal slew rate. PWRGD becomes high impedance approximately 5ms after CLKEN is pulled low. For GMCH applications (CLKEN = GND), PWRGD becomes high impedance approximately 60s after reaching the selected VID voltage. For automatic startup, the battery voltage should be present before VCC rises above its UVLO threshold. If the controller attempts to bring the output into regulation without the battery voltage present, the output undervoltage fault latch disables the controller. The MAX17528 remains shut down until the fault latch is cleared by toggling SHDN or cycling the VCC power supply below 0.5V.
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Figure 8. Pulse-Skipping/Discontinuous Crossover Point
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
If the VCC voltage drops below 4.25V, the controller assumes that there is not enough supply voltage to make valid decisions. To protect the output from overvoltage faults, the controller shuts down immediately and forces a high-impedance output (DL and DH pulled low) and pulls CSN low through a 10 discharge MOSFET.
VCC SHDN VID (D0-D6) SOFT-START 1/8 RTIME SLEW RATE 1.1V BOOT CPU CORE VOLTAGE INTERNAL PWM MODE CLKEN PWRGD tBLANK 60s typ NOTE: PGDIN = VCC. tBLANK 20s typ tBLANK 5ms typ PULSE SKIPPING FORCED-PWM MODE INVALID VID VALID VID INVALID VID
SOFT-SHUTDOWN 1/8 RTIME SLEW RATE
tBLANK 60s typ
Figure 9. IMVP-6.5 Power-Up and Shutdown Sequence Timing Diagram
VCC SHDN VID (D0-D6) SOFT-START 1/8 RTIME SLEW RATE GMCH CORE VOLTAGE INTERNAL PWM MODE PWRGD tBLANK 5ms typ PULSE SKIPPING FORCED-PWM VALID VID INVALID VID
SOFT-SHUTDOWN 1/8 RTIME SLEW RATE
tBLANK 60s typ
Figure 10. GMCH Power-Up and Shutdown Sequence Timing Diagram
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Table 3. Operating Mode Truth Table
SHDN GND SLOW X SKIP X DISABLED Pulse skipping 1/8 RTIME slew rate Forced-PWM nominal RTIME slew rate Pulse-skipping nominal RTIME slew rate OPERATING MODE LOW-POWER SHUTDOWN. DL forced low, and the controller is disabled. The supply current drops below 30A. STARTUP. When SHDN is pulled high, the MAX17528 begins the startup sequence after the internal circuitry powers up. The MAX17528 enables the PWM controller and ramps the output voltage up to the startup voltage. See Figures 9 and 10. FULL POWER. The no-load output voltage is determined by the selected VID DAC code (Table 2). LOW-POWER MODE (NOMINAL TRANSITION). The no-load output voltage is determined by the selected VID DAC code (Table 2). When SKIP is pulled high, the controller immediately enters pulse-skipping operation, allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN upper thresholds are blanked during the transition. LOW-POWER MODE (SLOW TRANSITION). The no-load output voltage is determined by the selected VID DAC code (Table 2). When SKIP is pulled high, the MAX17528 enters pulse-skipping operation, allowing automatic PWM/PFM switchover under light loads. The PWRGD and CLKEN thresholds are blanked during the transition. SHUTDOWN. When SHDN is pulled low, the MAX17528 immediately pulls PWRGD low, CLKEN becomes high impedance, and the output voltage is ramped down to ground. Once the output reaches zero, the controller enters the low-power shutdown state. See Figures 9 and 10. FAULT MODE. The fault latch has been set by the MAX17528 UVP fault, RTON open fault, or thermal-shutdown protection. The controller remains in FAULT mode until VCC power is cycled or SHDN toggled.
MAX17528
Rising
X
X
High
X
Low
High
High
High
High
Low
High
Pulse-skipping 1/2 RTIME slew rate
Falling
X
X
Forced-PWM 1/8 RTIME slew rate
High
X
X
DISABLED
Shutdown
When SHDN goes low, the MAX17528 enters lowpower shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down at 1/8 the slew rate set by RTIME: 8VOUT t TRAN(SHDN) = (dVTARGET / dt) where dVTARGET/dt = 12.5mV/s x 71.5k/RTIME is the nominal slew rate. Slowly discharging the output capacitors by slewing the output over a long period of time keeps the average negative inductor current low (damped response), thereby eliminating the negative output-voltage excursion that occurs when the controller discharges the output quickly by permanently turning on the low-side MOSFET (underdamped response). This eliminates the need for the Schottky diode connected between the output and ground to clamp the negative output-voltage excursion. After the controller reaches the zero target, the MAX17528 shuts down completely--
the drivers are disabled (DL and DH are pulled low)-- the internal reference turns off, and the supply currents drop to about 30A (max). When an output undervoltage fault condition activates the shutdown sequence, the protection circuitry sets the UVP fault latch to prevent the controller from restarting. To clear the fault latch and reactivate the controller, toggle SHDN or cycle VCC power below 0.5V.
Current Monitor (IMON)
The MAX17528 includes a unidirectional transconductance amplifier that sources current proportional to the positive current-sense voltage. The IMON output current is defined by: IIMON = Gm(IMON) x (VCSP - VCSN) where Gm(IMON) = 5mS (typ) and the IMON current is unidirectional (sources current out of IMON only) for positive current-sense values. For negative currentsense voltages, the IMON current is zero.
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
The current monitor allows the processor to accurately monitor the CPU load and quickly calculate the power dissipation to determine if the system is about to overheat before the significantly slower temperature sensor signals an overtemperature alert. Connect an external resistor between IMON and VSS_SENSE to create the desired IMON gain based on the following equation: RIMON = 0.999V/(IMAX x RSENSE x Gm(IMON)) where IMAX is defined in the Current Monitor section of the Intel IMVP-6.5 specification and based on discrete increments (10A, 20A, 30A, 40A, etc.,), RSENSE is the typical effective value of the current-sense element (sense resistor or inductor DCR) that is used to provide the current-sense voltage, and Gm(IMON) is the typical transconductance amplifier gain as defined in the Electrical Characteristics table. The IMON voltage is internally clamped to a maximum of 1.1V (typ), preventing the IMON output from exceeding the IMON voltage rating even under overload or short-circuit conditions. When the controller is disabled, IMON is pulled to ground. The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot directly drive large capacitance values. To filter the IMON signal, use an RC filter as shown in Figure 1.
MAX17528
Thermal Fault Protection The MAX17528 features a thermal-fault-protection circuit. When the junction temperature rises above +160C, a thermal sensor sets the fault latch, forces DL low, and pulls DH low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller after the junction temperature cools by 15C. Thermal shutdown can be disabled through the no-fault test mode (see the No-Fault Test Mode section). No-Fault Test Mode The latched fault-protection feature can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a "no-fault" test mode is provided to disable the fault protection--UVP, thermal shutdown, and TON open-circuit fault protection. The "no-fault" test mode also disables the BST switch, although the switch's body diode provides sufficient power for the high-side driver to function properly. Additionally, the test mode clears the fault latch if it has been set. The no-fault test mode is entered by forcing 11V to 13V on SHDN.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power MOSFETs. This is consistent with the low duty factor seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate drivers (DH) source and sink 2.2A, and the low-side gate drivers (DL) source 2.7A and sink 8A. This ensures robust gate drive for high-current applications. The DH high-side MOSFET driver is powered by an internal charge-pump boost switch at BST, while the DL synchronous-rectifier driver is powered directly by the 5V bias supply (VDD). Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the other is fully off. The adaptive driver dead time allows operation without shoot-through with a wide range of MOSFETs, minimizing delays and maintaining efficiency. There must be a low-resistance, low-inductance path from the DL and DH drivers to the MOSFET gates for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17528 interprets the MOSFET gates as "off" while charge actually remains. Use very short, wide traces (50 mils to 100 mils wide if the MOSFET is 1in from the driver).
Temperature Comparator (VRHOT)
The MAX17528 also features an independent comparator with an accurate threshold that tracks the analog supply voltage (VHOT = 0.3 x VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistor-divider between VCC and GND to generate a voltage-regulator overtemperature monitor. Place the thermistor as close as possible to the MOSFETs and inductors.
Output Undervoltage (UVP) Protection The output UVP function limits the power loss by disabling the regulator if the MAX17528 output voltage drops 400mV below the target voltage; the controller activates the shutdown sequence and sets the fault latch. Once the controller ramps down to zero, it forces DL high and DH low. Toggle SHDN or cycle the VCC power supply below 0.5V to clear the fault latch and reactivate the controller. UVP protection can be disabled through the no-fault test mode (see the No-Fault Test Mode section).
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The internal pulldown transistor that drives DL low is robust, with a 0.25 (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling from the drain to the gate of the low-side MOSFETs when the inductor node (LX) quickly switches from ground to VIN. Applications with high input voltages and long inductive driver traces must guarantee rising LX edges do not pull up the low-side MOSFET's gate, causing shoot-through currents. The capacitive coupling between LX and DL created by the MOSFET's gate-todrain capacitance (CRSS), gate-to-source capacitance (CISS - CRSS), and additional board parasitics should not exceed the following minimum threshold: C VGS(TH) < VIN RSS CISS Typically, adding a 4700pF between DL and power ground (C NL in Figure 11), close to the low-side MOSFETs, greatly reduces coupling. Do not exceed 22nF of total gate capacitance to prevent excessive turn-off delays. Alternatively, shoot-through currents can be caused by a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side MOSFET is too long, the high-side MOSFETs can turn on before the low-side MOSFETs have actually turned off. Adding a resistor less than 5 in series with BST slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading the turn-off time (RBST in Figure 11). Slowing down the high-side MOSFET also reduces the LX node rise time, thereby reducing EMI and high-frequency coupling responsible for switching noise.
DL (CNL)* PGND NL
MAX17528
MAX17528 BST
(RBST)* INPUT (VIN) CBST
DH LX
NH L
VDD
CBYP
(RBST)* OPTIONAL--THE RESISTOR LOWERS EMI BY DECREASING THE SWITCHING NODE RISE TIME. (CNL)* OPTIONAL--THE CAPACITOR REDUCES LX TO DL CAPACITIVE COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 11. Gate-Drive Circuit
*
Quick-PWM Design Procedure
Firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). The primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following five factors dictate the rest of the design: * Input voltage range: The maximum value (VIN(MAX)) must accommodate the worst-case high AC adapter voltage. The minimum value (VIN(MIN)) must account for the lowest input voltage after drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input voltages result in better efficiency.
Maximum load current: There are two values to consider. The peak load current (I LOAD(MAX) ) determines the instantaneous component stresses and filtering requirements, and thus, drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal stresses, and thus, drives the selection of input capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%. Load line (voltage positioning): The load line (output voltage vs. load slope) dynamically lowers the output voltage in response to the load current, reducing the output capacitance requirement and the processor's power dissipation. The Intel specification clearly defines the load-line requirement in the powersupply specifications for each processor family.
*
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
* Switching frequency: This choice determines the basic trade-off between size and efficiency. The optimal frequency is largely a function of maximum input voltage due to MOSFET switching losses that are proportional to frequency and VIN2. The optimum frequency is also a moving target due to rapid improvements in MOSFET technology that are making higher frequencies more practical. Inductor operating point: This choice provides trade-offs between size vs. efficiency and transient response vs. output noise. Low inductor values provide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. The minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduction (where the inductor current just touches zero with every cycle at maximum load). Inductor values lower than this grant no further size-reduction benefit. The optimum operating point is usually found between 20% and 50% ripple current. VOUT tSW M + tOFF(MIN) VIN VSAG = ( VIN - VOUT ) tSW 2COUT VOUT - tOFF(MIN) VIN L ILOAD(MAX)
(
)2
*
where t OFF(MIN) is the minimum off-time (see the Electrical Characteristics table). The amount of overshoot due to stored inductor energy can be calculated as: VSOAR
(ILOAD(MAX) )2L
2COUT VOUT
Current-Limit and Slew-Rate Control (TIME and ILIM)
TIME and ILIM are used to control the slew rate and current limit. TIME regulates to a fixed 2.0V. The MAX17528 uses the TIME source current to set the slew rate (dVTARGET/dt). The higher the source current, the faster the nominal output-voltage slew rate: 71.5k dVTARGET / dt = 12.5mV / s x RTIME where RTIME is the sum of resistance values between TIME and ground. The ILIM voltage determines the valley current-sense threshold. When ILIM = VCC, the controller uses the preset 22.5mV (typ) current-limit threshold. In an adjustable design, ILIM is connected to a resistive voltage-divider connected between TIME and ground. The differential voltage between TIME and ILIM sets the current-limit threshold (VLIMIT), so the valley currentsense threshold is: V -V VLIMIT = TIME ILIM 10 where the VLIMIT tolerances are defined in the Electrical Characteristics table. This allows design flexibility since the DCR sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mV. Keeping VLIMIT between 20mV to 40mV leaves room for future current-limit adjustment.
Inductor Selection
The switching frequency and operating point (% ripple current or LIR) determine the inductor value as follows: V VIN - VOUT OUT L= fSWILOAD(MAX)LIR VIN Find a low-loss inductor having the lowest possible DC resistance that fits in the allotted dimensions. Molded cores are often the best choice, although powdered iron and ferrite cores are inexpensive and can work well at 300kHz. The core must be large enough not to saturate at the peak inductor current (IPEAK): LIR IPEAK = ILOAD(MAX) 1 + 2
Transient Response
The inductor ripple current impacts transient-response performance, especially at low VIN - VOUT differentials. Low inductor values allow the inductor current to slew faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. The worst-case output sag voltage can be determined by:
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
The minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus half the ripple current; therefore: LIR IVALLEY > ILOAD(MAX) 1 - 2 where: IVALLEY = VLIMIT VLIMIT = RSENSE DCR x RCSP-CSN RLX -CSN In CPU VCORE converters and other applications where the output is subject to large-load transients, the output capacitor's size typically depends on how much ESR is needed to prevent the output from dipping too low under a load transient. Ignoring the sag due to finite capacitance:
MAX17528
(RESR + RPCB ) I
VSTEP
LOAD(MAX)
where RSENSE is the sensing resistor and RCSP-CSN/ R LX-CSN is the ratio of resistor-divider with DCRsensing approach.
In non-CPU applications, the output capacitor's size often depends on how much ESR is needed to maintain an acceptable level of output ripple voltage. The output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitor's ESR. The maximum ESR to meet ripple requirements is: VINfSWL RESR VRIPPLE (VIN - VOUT )VOUT where f SW is the switching frequency. The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value (this is true of polymer types). When using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent V SAG and V SOAR from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the VSAG and VSOAR equations in the Transient Response section).
Voltage Positioning and Loop Compensation
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor's power dissipation requirements. The controller uses a transconductance amplifier to set the transient and DC output voltage droop (Figure 3) as a function of the load. This adjustability allows flexibility in the selected current-sense resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall power dissipated.
Steady-State Voltage Positioning Connect a resistor (RFB) between FB and VOUT to set the DC steady-state droop (load line) based on the required voltage-positioning slope (RDROOP):
RFB = RDROOP RSENSEGm(FB)
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation: f fESR SW where: fESR = and: REFF = RESR + RDROOP + RPCB where COUT is the total output capacitance, RESR is the total ESR, RDROOP is the voltage-positioning slope, and
37
where the effective current-sense resistance (RSENSE) depends on the current-sense method (see the Current Sense section), and the voltage-positioning amplifier's transconductance (G m(FB) ) is typically 600S as defined in the Electrical Characteristics table. When the inductors' DCR is used as the current-sense element (R SENSE = R DCR), the current-sense design should include a thermistor to minimize the temperature dependence of the voltage-positioning slope as shown in Figure 1.
1 2REFFCOUT
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and load-transient requirements, yet have high enough ESR to satisfy stability requirements.
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
RPCB is the parasitic board resistance between the output capacitors and sense resistors. For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below 50kHz. Tantalum, SANYO POSCAP, and Panasonic SP capacitors in widespread use at the time of publication have typical ESR zero frequencies below 50kHz. In the standard GMCH application circuit, the ESR needed to support a 10mVP-P ripple is 10mV/(10A x 0.3) = 3.3m. Two 330F/2.5V Panasonic SP (type SX) capacitors in parallel provide 3.0m (max) ESR. With a 5m droop and 0.5m PCB resistance, the typical combined ESR results in a zero at 28kHz. Ceramic capacitors have a high-ESR zero frequency, but applications with significant voltage positioning can take advantage of their size and low ESR. Do not put high-value ceramic capacitors directly across the output without verifying that the circuit contains enough voltage positioning and series PCB resistance to ensure stability. When only using ceramic output capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement. Their relatively low capacitance value can cause output overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high switching frequency) to minimize the energy transferred from inductor to capacitor during load-step recovery. Unstable operation manifests itself in two related, but distinctly different ways: double pulsing and feedback loop instability. Double pulsing occurs due to noise on the output or because the ESR is so low that there is not enough voltage ramp in the output voltage signal. This "fools" the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. Double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop instability can result in oscillations at the output after line or load steps. Such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. The easiest method for checking stability is to apply a very fast zero-to-max load transient and carefully observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor the inductor current with an AC current probe. Do not allow more than one cycle of ringing after the initial step-response under/overshoot.
Input Capacitor Selection
The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. The IRMS requirements can be determined by the following equation: I IRMS = LOAD VOUT (VIN - VOUT ) VIN The worst-case RMS current requirement occurs when operating with VIN = 2 x VOUT. At this point, the above equation simplifies to IRMS = 0.5 x ILOAD. For most applications, nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a mechanical switch or connector in series with the input. If the Quick-PWM controller is operated as the second stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than +10C temperature rise at the RMS input current for optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention. The high-side MOSFET (NH) must be able to dissipate the resistive losses plus the switching losses at both VIN(MIN) and VIN(MAX). Calculate both of these sums. Ideally, the losses at VIN(MIN) should be roughly equal to losses at VIN(MAX), with lower losses in between. If the losses at VIN(MIN) are significantly higher than the losses at VIN(MAX), consider increasing the size of NH (reducing RDS(ON) but with higher CGATE). Conversely, if the losses at VIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of NH (increasing RDS(ON) to lower CGATE). If VIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two 8-pin SOs, DPAK, or D2PAK), and is reasonably priced. Make sure that the DL gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Drivers section).
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the minimum input voltage: V 2 PD(NHRe sistive) = OUT (ILOAD ) RDS(ON) VIN Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package power dissipation often limits how small the MOSFET can be. Again, the optimum occurs when the switching losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue until the input is greater than approximately 15V. Calculating the power dissipation in high-side MOSFET (NH) due to switching losses is complicated since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on NH:
QG(SW) COSSVIN2fSW PD(NHSwitching) = VIN(MAX)ILOADfSW + 2 IGATE
ILOAD(MAX), but are not quite high enough to exceed the current limit and cause the fault latch to trip. To protect against this possibility, you can "over design" the circuit to tolerate: I ILOAD = IVALLEY(MAX) + INDUCTOR = IVALLEY(MAX) 2 where I VALLEY(MAX) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. The MOSFETs must have a good-size heatsink to handle the overload power dissipation. Choose a Schottky diode (DL) with a forward voltage low enough to prevent the low-side MOSFET body diode from turning on during the dead time. Select a diode that can handle the load current during the dead times. This diode is optional and can be removed if efficiency is not critical.
MAX17528
Boost Capacitors
The boost capacitors (CBST) must be selected large enough to handle the gate-charging requirements of the high-side MOSFETs. Typically, 0.1F ceramic capacitors work well for low-power applications driving medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost capacitors larger than 0.1F. For these applications, select the boost capacitors to avoid discharging the capacitor more than 200mV while charging the highside MOSFETs' gates: CBST = N x QGATE 200mV
where COSS is the NH MOSFET's output capacitance, QG(SW) is the charge needed to turn on the NH MOSFET, and IGATE is the peak gate-drive source/sink current (2.2A typ). Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the C x VIN2 x fSW switching-loss equation. If the high-side MOSFET chosen for adequate RDS(ON) at low battery voltages becomes extraordinarily hot when biased from V IN(MAX) , consider choosing another MOSFET with lower parasitic capacitance. For the low-side MOSFET (NL), the worst-case power dissipation always occurs at maximum input voltage:
V 2 PD(NL Re sistive) = 1 - OUT (ILOAD ) RDS(ON) VIN(MAX)
where N is the number of high-side MOSFETs used for one regulator, and QGATE is the gate charge specified in the MOSFET's data sheet. For example, assume (2) IRF7811W n-channel MOSFETs are used on the high side. According to the manufacturer's data sheet, a single IRF7811W has a maximum gate charge of 24nC (VGS = 5V). Using the above equation, the required boost capacitance would be: CBST = 2 x 24nC = 0.24F 200mV
Selecting the closest standard value, this example requires a 0.22F ceramic capacitor.
The worst case for MOSFET power dissipation occurs under heavy overloads that are greater than
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers MAX17528
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all the power components on the top side of the board with their ground terminals flush against one another. Follow the MAX17528 Evaluation Kit layout and use the following guidelines for good PCB layout: * High-current path/components: Keep the high-current paths short, especially at the ground terminals. This is essential for stable, jitter-free operation. Keep the power traces and load connections short. This is essential for high efficiency. The use of thick copper PCBs (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. Correctly routing PCB traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m of excess trace resistance causes a measurable efficiency penalty. When trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. For example, it is better to allow some extra distance between the input capacitors and the high-side MOSFET than to allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor. MOSFET drivers: Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide to minimize trace resistance and inductance. This is essential for high-power MOSFETs that require low-impedance gate drivers to avoid shootthrough currents. Analog control signals: Connect all analog grounds to a separate solid copper plane, which connects to the GND pin of the Quick-PWM controller as shown in Figures 1 and 2. This includes the VCC bypass capacitor, remote-sense bypass capacitors, and the compensation (CCV) components. * * CSP and CSN connections for current limiting and voltage positioning must be made using Kelvinsense connections to guarantee the current-sense accuracy. Route high-speed switching nodes (LX, DH, BST, and DL) away from sensitive analog areas (FB, CSP, CSN, CCV, etc.).
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN, COUT, and D1 anode). If possible, make all these connections on the top layer with wide, copperfilled areas. 2) Mount the controller IC adjacent to the low-side MOSFET. The DL gate traces must be short and wide (50 mils to 100 mils wide if the MOSFET is 1in from the controller IC). 3) Group the gate-drive components (BST capacitor, VDD bypass capacitor) together near the controller IC. 4) Make the DC-DC controller ground connections as shown in the standard application circuits. This diagram can be viewed as having three separate ground planes: input/output system ground, where all the high-power components go; the power ground plane, where the PGND pin and V DD bypass capacitor go; and the controller's analog ground plane where sensitive analog components, the analog GND pin, and VCC bypass capacitor go. The analog GND plane must meet the PGND plane only at a single point directly beneath the controller. This star ground point (where the power and analog grounds are connected) should connect to the high-power system ground with a low-impedance connection (short trace or multiple vias) from PGND to the source of the low-side MOSFET. 5) Connect the output power planes (VCORE and system ground planes) directly to the output filter capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit as close as is practical to the CPU.
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1-Phase Quick-PWM Intel IMVP-6.5/GMCH Controllers
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE 32 TQFN
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE CODE T3255-3 DOCUMENT NO. 21-0140
MAX17528
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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